Copper metallization is increasingly being used for advanced product integrated circuit fabrication including semiconductor features from sub-micron high aspect ratio interconnect features to larger features such as bonding pads. Copper and its alloys have lower resistivity and better electromigration resistance compared to other metals such as, for example, aluminum. These characteristics are critical for achieving higher current densities with increased device speed. While several processing difficulties related to forming copper semiconductor features have been overcome, several problems remain especially in back-end-of-line (BEOL) manufacturing processes. BEOL processes have traditionally addressed the problems of surface contaminants that adversely affect adhesion of overlying layers, contact formation, and chemical mechanical polishing (CMP).
One exemplary process for forming a multiple level semiconductor device includes, for example, is a dual damascene process. Although there are several different manufacturing methods for manufacturing dual damascene structures, all such methods employ at least two photolithographic masking and anisotropic etching steps, for example, first forming vias to electrically interconnect different levels followed by the formation of an overlying trench at least partially encompassing one or more vias to provide electrical interconnection between multiple device levels and within a device level. In most devices, pluralities of vias are separated from one another along the semiconductor wafer and selectively interconnect conductive regions between layers of a multi layer device. Metal interconnect lines or trench lines typically serve to selectively interconnect conductive regions within a layer of a multilayer device. Dual damascene formation is a process whereby via openings and trench line openings are formed in a dielectric insulating layer to form a dual damascene structure followed by a metal deposition process to fill the dual damascene structure to form the necessary electrical connections.
In forming a copper semiconductor feature, typically a relatively pure (undoped) copper material is deposited to fill an anisotropically etched opening, for example a dual damascene structure. Copper electro-chemical plating (ECP) is a preferable method for depositing copper to achieve superior step coverage of sub-micron etched features. ECP generally includes depositing a copper seed layer over the barrier layer and then electroplating bulk copper over the seed layer to fill the etched feature to form, for example, vias and trench lines. The deposited copper layer is then planarized to remove excess copper overlying the feature level by chemical mechanical polishing (CMP).
One problem affecting BEOL processes in copper metallization is the tendency of copper to easily form oxides of copper, for example (CuO or CuO2) upon exposure to oxidizing environments including humid environments. Since ECP deposited bulk polycrystalline copper includes a network of grain boundaries running through the bulk of the copper filled feature, oxidation is particularly harmful to ECP deposited copper since copper oxide formation will tend to penetrate into the bulk of the copper through grain boundaries. As a result, it has become essential to carry out a post ECP copper CMP process as soon as possible following the ECP copper deposition to avoid copper oxide induced degradation of the copper features. For example, the formation of copper oxide within the bulk of the copper along the grain boundaries has a severely detrimental effect on the electrical resistance and electromigration resistance of the copper feature adversely affecting wafer yield and reliability.
In addition, the necessity of carrying out the post ECP CMP process prior to significant copper oxide formation places costly restraints on manufacturing processes, limiting a wafer throughput due to available manufacturing resources.
Yet other problems related to copper oxide formation includes reduced adhesion of copper to adjacent layers within the feature such as a barrier layer and contributes to copper hillock formation (surface protrusions) during subsequent thermal processes.
These and other shortcomings in copper feature manufacturing processes demonstrate a need in the semiconductor processing art to develop a method for forming multiple layer devices including copper metallization where copper oxidation is avoided between manufacturing processes thereby improving device performance and improving a manufacturing process.
It is therefore an object of the invention to provide a method for forming multiple layer devices including copper metallization where copper oxidation is avoided between manufacturing processes thereby improving device performance and improving a manufacturing process.